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DIRECS: system design of a 100 Mbit/s digital receiver

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4 Author(s)
Joeressen, O. ; Aachen Univ. of Technol., Germany ; Oerder, M. ; Serra, R. ; Meyr, H.

The advances in VLSI technology have made the digital implementation of data receivers feasible at very high data rates. Aspects of the design of a chip set representing a 100 Mbit/s digital receiver for coded 8-PSK modulation are described. The receiver is discussed as an example of complex system design and finally implementation aspects are presented. Special emphasis is given to design methodology, trade-off optimisation and performance results. Attention is paid to the structural and algorithmic design as an integral part of the implementation process to obtain an efficient solution

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Circuits, Devices and Systems, IEE Proceedings G  (Volume:139 ,  Issue: 2 )