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Fabrication and characteristics of novel load PMOS SSTFT (Stacked Single-crystal Thin Film Transistor) for 3-Dimensional SRAM memory cell

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16 Author(s)
Kang, Y.H. ; R&D Centre, Samsung Electron. Co. Ltd., Kyungki, South Korea ; Jung, S. ; Jang, J.H. ; Moon, J.H.
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The PMOS SSTFT (stacked single-crystal thin film transistor) is developed for achieving the smallest SRAM cell size, such as 45F2, and low power mobile applications with the single crystallization technology of the Si thin films on the insulators. The electrical properties of the SSTFT load pMOS are comparable to those of bulk Si Tr. or SOI Tr. For example, Ion/Ioff ratio is nearly 107 and sub-threshold swing is 150 mV/dec. The SNM(Static Noise Margin) value is 650 mV at Vdd=2.0 V and the SSTFT load pMOS lifetime under the HElP stress is over 10 years at 3.0 V operation voltage. The novel S3 (stacked single-crystal Si) SRAM cell used the SSTFT pMOS as the load pMOS which is successfully fabricated.

Published in:

SOI Conference, 2004. Proceedings. 2004 IEEE International

Date of Conference:

4-7 Oct. 2004