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Enhanced high resistivity SOI wafers for RF applications

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3 Author(s)
Lederer, D. ; Microwave Lab., Univ. Catholique de Louvain, Belgium ; Lobet, R. ; Raskin, J.P.

In this work, we investigate the impact of distinctly processed trap-rich layers of polysilicon inserted between BOX and HR Si substrate on the effective resistivity, substrate losses and crosstalk level in HR SOI wafers. The wafers were fabricated starting from p-type high resistivity bulk wafers with resistivity higher than 3 kΩ.cm. The wafers were first covered with a LPCVD layer of undoped polysilicon at 2 distinct temperatures (Tpoly=585 °C, 625 °C) and with varying thickness. This layer was afterwards passivated with a charge rich 3 μm thick PECVD oxide of the reference wafer. The oxide layer was densified by RTA at 800 °C during 20 s.

Published in:

SOI Conference, 2004. Proceedings. 2004 IEEE International

Date of Conference:

4-7 Oct. 2004