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Design and optimization of vertical SiGe thyristors for on-chip ESD protection

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3 Author(s)
S. Joshi ; Univ. of Illinois, Urbana, IL, USA ; R. Ida ; E. Rosenbaum

We present extensive measurement results investigating the design and optimization of vertical SiGe thyristors for use as ESD protection elements in RF integrated circuits. Experiments include variations of the anode material, contact geometry, and buried layer, as well as a detailed study of optimal area scaling. RF characterization using S-parameter data is presented.

Published in:

IEEE Transactions on Device and Materials Reliability  (Volume:4 ,  Issue: 4 )