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High-performance low-power left-to-right array multiplier design

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2 Author(s)
Huang, Z. ; Magma Design Autom. Inc., Santa Clara, CA, USA ; Ercegovac, M.D.

We present a high-performance low-power design of linear array multipliers based on a combination of the following techniques: signal flow optimization in [3:2] adder array for partial product reduction, left-to-right leapfrog (LRLF) signal flow, and splitting of the reduction array into upper/lower parts. The resulting upper/lower LRLF (ULLRLF) multiplier is compared with tree multipliers. From automatic layout experiments, we find that ULLRLF multipliers have similar power, delay, and area as tree multipliers for n≤32. With more regularity and inherently shorter interconnects, the ULLRLF structure presents a competitive alternative to tree structures in the design of fast low-power multipliers implemented in deep submicron VLSI technology.

Published in:

Computers, IEEE Transactions on  (Volume:54 ,  Issue: 3 )

Date of Publication:

March 2005

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