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Scalable hardware memory disambiguation for high-ILP processors

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5 Author(s)

Power is a major problem for scaling the hardware needed to support memory disambiguation in future out-of-order architectures. In current machines, the traditional detection of memory ordering violations requires frequent associative searches of state proportional to the instruction window size. A new class of solutions yields an order-of-magnitude reduction in the energy required to properly order loads and stores for windows of hundreds to thousands of in-flight instructions

Published in:

Micro, IEEE  (Volume:24 ,  Issue: 6 )