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Reducing the soft-error rate of a high-performance microprocessor

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4 Author(s)

Single-bit upsets from transient faults have emerged as a key challenge in microprocessor design. Soft errors will be an increasing burden for microprocessor designers as the number of on-chip transistors continues to grow exponentially. Unlike traditional approaches, which focus on detecting and recovering from faults, this article introduces techniques to reduce the probability that a fault will cause a declared error. The first approach reduces the time instructions sit in vulnerable storage structures. The second avoids declaring errors on benign faults. Applying these techniques to a microprocessor instruction queue significantly reduces its error rate with only minor performance degradation

Published in:

Micro, IEEE  (Volume:24 ,  Issue: 6 )

Date of Publication:

Nov.-Dec. 2004

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