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Interconnect test pattern generation algorithm for meeting device and global SSO limits with safe initial vectors

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2 Author(s)
Baker, K. ; Raytheon Co., Plano, TX, USA ; Nourani, M.

This work presents a method of creating a true/complement pattern set of optimal size that satisfies simultaneous switching limit constraints. This method is an improvement over previous methods in that it has better runtime characteristics as well as the ability to handle additional scenarios. It can produce safe initial vectors, produce vectors that consider switching limits by device rather than globally, and reduce (or eliminate) the number of morph vectors required.

Published in:

Test Conference, 2004. Proceedings. ITC 2004. International

Date of Conference:

26-28 Oct. 2004