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A new arbitration circuit for synchronous multiple bus multiprocessor systems

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2 Author(s)
S. M. Mahmud ; Dept. of Electr. & Comput. Eng., Wayne State Univ., Detroit, MI, USA ; M. Showkat-Ul-Alam

A novel design for an M-user B-server arbiter for a multiple bus system is presented. The arbitration circuit maintains fairness when it is used in a low-order interleaved memory system. The arbiter is also fair for a general-purpose multiprocessor system where the memory modules are uniformly accessed by the processors. The arbitration time grows at a rate O(log2 M), where M is the number of memory modules in a system. When a system has more than four memory modules, both the gate count and delay of the present design are less than those of previous designs

Published in:

Systems Integration, 1990. Systems Integration '90., Proceedings of the First International Conference on

Date of Conference:

23-26 Apr 1990