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The Aquarius-IIU system

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5 Author(s)
D. R. Busing ; Div. of Comput. Sci., California Univ., Berkeley, CA, USA ; V. P. Srini ; G. E. Smine ; M. J. Carlton
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A description is given of Aquarius IIU, a complex system integrating a high-performance symbolic microprocessor, an instruction prefetcher, snooping data and instruction caches, a VME bus interface, and a set of controllers. Aquarius IIU is based on the high performance VLSI-PLM chip that runs the Warren abstract machine instruction set. Many of these nodes have been connected using a shared bus to form a multiprocessor which has its own shared memory and snooping caches and is used as a backend Prolog engine to the host (SUN3/160). On every node, there are two controllers per data and instruction cache that cooperate to support Berkeley's snooping cache-lock state protocol, which minimizes bus traffic associated with locking blocks. The nodes share memory using the signals of the VME bus; the page faults and memory management are handled by the host. A top-down method was used in the design of the Aquarius IIU node, while a bottom-up method was used in the simulations. In designing and simulating complex systems such as the Aquarius IIU, the procedure followed was found to be advantageous

Published in:

Systems Integration, 1990. Systems Integration '90., Proceedings of the First International Conference on

Date of Conference:

23-26 Apr 1990