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We present here an extensive static random access memory (SRAM) bitcell development methodology that has led to the qualification and production of the smallest 6-T SRAM bitcell reported in 0.13-μm CMOS technology. No additional processing steps were employed in accomplishing this result. Such a methodology is being extended also to subsequent technology generations. The development efforts included the electrical evaluation of several candidate 6-T SRAM bitcell architectures for both high-density and high-speed applications. Based on the electrical evaluations, the chosen cell architectures were incorporated in silicon and verified for their robustness with respect to critical design rules, yields and reliability. The methodology for optical proximity correction for bitcell development has been described here. Minor process enhancements to ensure compatibility of the overall process flow with the SRAM bitcells are described. The use of SRAM-specific electrical test structures serves an important role in validating the electrical performance and confirming the robustness of the bitcells in a manufacturing environment. The monitoring of Vddmin, the minimum voltage at which the memory is functional was used to drive overall process improvements and reliability. Lastly, measurements of soft error rates demonstrated excellent immunity of the bitcells to single event upsets.
Date of Publication: Feb. 2005