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On masking of redundant faults in synchronous sequential circuits with design-for-testability logic

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2 Author(s)
I. Pomeranz ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; S. M. Reddy

Design for testability (DFT) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. In this paper, we propose to deal with such faults by masking (or ignoring) their fault effects when they appear on the circuit outputs. This should be done without masking the detection of other faults of the original circuit, which need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of masked faults among the faults that should be detected.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:24 ,  Issue: 2 )