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VLSI implementation of new arithmetic residue to binary decoders

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1 Author(s)
Hiasat, A.A. ; Comput. Eng. Dept., Princess Sumaya Univ. for Technol., Amman, Jordan

This paper introduces two arithmetic decoders that decode the residue number system into its binary equivalent. The first one deals with the moduli set: (2/sup n/,2/sup n/-1,2/sup n/+1,2/sup n/-2/sup (n+1/2)/+1,2/sup n/+2/sup (n+1/2)/+1), while the other deals with the moduli set: (2/sup n+1/,2/sup n/-1,2/sup n/+1,2/sup n/-2/sup (n+1/2)/+1,2/sup n/+2/sup (n+1/2)/+1), where n is odd. Compact forms for the multiplicative inverse of each modulus is introduced, which facilitates the implementation of these arithmetic decoders. The proposed hardware realizations for these decoders are based on using six carry save adders and one carry propagate adder. The hardware and time requirements of these decoders are much better than other similar decoders found in literature. A sub-micron silicon implementation for the decoder has been performed and reported.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:13 ,  Issue: 1 )