By Topic

Deterministic Hardware Synthesis for Compiling High-Level Descriptions to Heterogeneous Reconfigurable Architectures

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)

LUT based reconfigurability is being complemented with a new, emerging class of reconfigurable technology based on ALU and heterogeneous architectures. Moreover, existing FPGA technology has experienced recent advances that go beyond other implementation technologies such as DSP, ASIC or ASSP. Already deployed within the network infrastructure and application areas where performance, power and flexibility are principal, the migration of software-programmed hardware reconfigurability to the mobile computing domain is attractive. To enable this migration an advance in design automation is required where algorithms can be efficiently mapped to the computational fabric using software-programming techniques. In this paper we describe how digital circuits from software designs and formal executable specifications can be synthesized to reconfigurable architectures using higher-level languages and deterministic hardware compilation, or 'C-synthesis'. For context we provide an introduction and overview to reconfigurable architectures.

Published in:

System Sciences, 2005. HICSS '05. Proceedings of the 38th Annual Hawaii International Conference on

Date of Conference:

03-06 Jan. 2005