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Power monitors: a framework for system-level power estimation using heterogeneous power models

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4 Author(s)
Bansal, N. ; NEC Labs. America, Princeton, NJ, USA ; Lahiri, K. ; Raghunathan, A. ; Chakradhar, S.T.

Power analysis early in the design cycle is critical for the design of low power systems. With the move to system-level specifications and design methodologies, there has been significant research interest in system-level power estimation. However, as demonstrated in this paper, the addition of power estimation capabilities to system-level simulation tools can significantly degrade simulation efficiency (up to 8.5×), limiting the use of power estimation during long simulation rum, and the ability to perform extensive design space exploration. Some power modeling techniques for system components provide "local" tradeoffs between power estimation accuracy and computational cost This work addresses a complementary problem - the optimized integration and usage of heterogeneous component power models within a system-level simulation framework. We view system-level power estimation as a global deployment of computational effort (the effort required to perform power estimation) over space (the different components) and time (the duration of the simulation). We illustrate the advantages of optimizing the allocation of power estimation effort based on run-time variations of component-level, as well as system-level power consumption characteristics. To achieve this, we have developed a novel power estimation framework, based on a network of power monitors. Power monitors observe component- and system-level execution and power statistics at run time, based on which they (I) select between multiple alternative power models for each component, and/or (II) configure the component power models, to best negotiate the trade-off between efficiency and accuracy. In effect, the power monitor network performs a coordinated, adaptive, spatio-temporal allocation of computational effort for power estimation. Experiments conducted on a commercial system-level simulation framework and system-on-chip platform demonstrate that the proposed techniques yield large reductions in power estimation overhead (nearly an order of magnitude), while minimally impacting power estimation accuracy.

Published in:

VLSI Design, 2005. 18th International Conference on

Date of Conference:

3-7 Jan. 2005