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Most of the work done in the field of machine code compression is for fixed length instruction encodings. In this work we apply code compression on variable length instruction set processors whose encodings are already optimized to a certain extent with respect to their usages. We develop a dictionary based algorithm which utilizes unused encoding space of an instruction set architecture to encode code-words, and addresses issues arising out of variable length instructions. We test the algorithm with a RISC processor and include results for compression and performance in terms of cycle-counts and memory accesses respectively. We also present an efficient scheme for searching relocated branch addresses and analyze its performance.
VLSI Design, 2005. 18th International Conference on
Date of Conference: 3-7 Jan. 2005