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Design of multi-GHz asynchronous pipelined circuits in MOS current-mode logic

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2 Author(s)
Kwan, T.W. ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; Shams, M.

This paper introduces the implementation of asynchronous pipelined circuits in MOS current-mode logic (MCML). C-element and double-edge-triggered flip-flop are implemented in MCML and used in so-called micropipeline circuits. The effects of different layout techniques on the performance and power dissipation of an MCML FIFO are also investigated. Based on post-layout simulation results, an asynchronous MCML four-stage FIFO implemented in a standard 0.18 μm CMOS technology demonstrates a throughput of 4 GHz while dissipating 3.7 mW. The MCML micropipeline C-element dissipates up to four times less power compared to its conventional static CMOS counterpart at the same throughput of 1.9 GHz.

Published in:

VLSI Design, 2005. 18th International Conference on

Date of Conference:

3-7 Jan. 2005