Skip to Main Content
This paper introduces the implementation of asynchronous pipelined circuits in MOS current-mode logic (MCML). C-element and double-edge-triggered flip-flop are implemented in MCML and used in so-called micropipeline circuits. The effects of different layout techniques on the performance and power dissipation of an MCML FIFO are also investigated. Based on post-layout simulation results, an asynchronous MCML four-stage FIFO implemented in a standard 0.18 μm CMOS technology demonstrates a throughput of 4 GHz while dissipating 3.7 mW. The MCML micropipeline C-element dissipates up to four times less power compared to its conventional static CMOS counterpart at the same throughput of 1.9 GHz.