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In deep submicron technology (DSM), many defects cause relatively small delay faults that are hard to detect, but can cause functional and/or reliability failure. The mechanisms behind these delay defects can be varied and complex. Resistive interconnect defects, including those due to contamination or voids in vias, are among the more common defects observed in DSM designs, as are transistor defects such as gate oxide shorts. Even when electrical defect diagnosis is able to identify the delay defect location down to the failing node, traditional test methods are unable to differentiate between delays caused by a resistive interconnect and those due to weak transistor defects. This differentiation is important for gathering accurate defect statistics for process improvement during yield ramp-up. We combine the new DDSI delay test methodology that detects delays within the slack interval with variable voltage testing to characterize the delay defects. This new method can differentiate resistive interconnect delay defects from other nonresistive defects such as transistor faults. Experimental results are presented to confirm the effectiveness of the new method.
VLSI Design, 2005. 18th International Conference on
Date of Conference: 3-7 Jan. 2005