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Summary form only given. Just as the semiconductor industry has begun to ship production products at 90nm we find ourselves starting "pipe cleaner" designs at 65nm. Each process generation provides both opportunities and challenges to design teams and the 65nm node is no exception. This paper provides a short overview of the challenges of designing at 65nm with special emphasis on the relationship of the design process to the manufacturing process and what is changing in the way that design tools keep complexity at bay in a world where power density and process variability threaten to drive us off of Moore's now famous law.