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Recent advances in verification, equivalence checking & SAT-solvers

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3 Author(s)
D. Pradhan ; Dept. of Comput. Sci., Bristol Univ., UK ; M. Abadir ; M. Varea

Design flow, RTL-verification, simulation-based techniques, basic concepts of equivalence checking, combinational equivalence checking, ATPG-based techniques, compare point matching, mitering, don't cares, solver overview (structural verification, BDD-based solvers, SAT-based solvers), decision diagrams (BDDs, zBDDs, word-level DDs). Also covered are concepts in SAT solvers (backtrack-search algorithm, effective techniques, including nonchronological backtracking & Boolean constraint propagation), new EDA-related techniques (covering immediate implications, partial-clauses, local decisions & partial clauses). Finally, the tutorial gives an overview of various commercially available tools, & their applicability. Also discussed are future challenges, such as design for verifiability & potential new directions.

Published in:

18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design

Date of Conference:

3-7 Jan. 2005