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Today's deep sub-micron semiconductor technology has enabled large-scale integration of multi-million gates consisting of reusable intellectual property (IP), on-chip memory and user-defined logic on a single chip. The design of such SoC has introduced several challenges in terms of increased design complexity in the areas of functional verification, timing closure, physical design, signal integrity, reliability, manufacturing test and package design. This tutorial discusses a methodology that is based on the successful design of several digital dominated SoCs such as high-speed low-cost communications processors, VOP and DSL devices, high performance audio and video processors at Texas Instruments. It provides a complete breadth of digital chip design techniques. In addition, it covers some issues related to mixed-signal SoC and hierarchical design. Design tradeoffs are discussed to handle the SoC complexity, and yet meet the time-to-market demands. We review different methodologies that are followed in the industry to design these chips. Following topics are covered with examples to explain design challenges and the approaches used to address them: design planning; functional verification; design for test (DFT); synthesis, floor-planning and STA; design closure; manufacturing tests and future challenges.
VLSI Design, 2005. 18th International Conference on
Date of Conference: 3-7 Jan. 2005