By Topic

High-speed interconnect technology: on-chip and off-chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Sapatnekar, S. ; Minnesota Univ., Minneapolis, MN, USA ; Roychowdhury, J. ; Harjani, R.

Computing needs for business, communications and gaming applications continue to increase. Innovative IC processing and fabrication techniques developed by researchers from around the globe have allowed microprocessor manufacturers to continue their technology scaling trends such that current processors have hundreds of millions of transistors and have clock rates in multiple giga-Hertz. However, interconnect delays, both on-chip and off-chip, are quickly becoming the bottleneck and will limit the maximum performance attainable from device scaling. On-chip RC and RLC delays are becoming significantly larger than gate delays, forcing circuit designers to alter basic design methodologies and system designers to alter traditional architectures and design paradigms. This tutorial provides both timely and relevant information for both on-chip and off-chip interconnect technologies. Topics covered in this tutorial include on-chip wire modeling, delay calculations, optimization and design techniques; off-chip interconnect and cross-talk modeling, high-speed I/O transceivers and drivers, binary and multi-level signaling, clock and data recovery circuits, jitter and phase noise modeling. The speakers bring both academic and industrial experience to bear on this critical topic. The tutorial is aimed at senior students and practicing engineers interested in high-performance circuit designs.

Published in:

VLSI Design, 2005. 18th International Conference on

Date of Conference:

3-7 Jan. 2005