By Topic

A general framework for probabilistic low-power design space exploration considering process variation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
A. Srivastava ; Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA ; D. Sylvester

Increasing levels of process variation in current process technologies make it extremely important that design and process decisions be made while considering their impact. This work presents a convex optimization based approach to select supply and threshold voltages to minimize power dissipation in generic multi-Vdd/Vth CMOS designs while considering process variation. We use this probabilistic approach to compare the optimization of different statistical parameters of power dissipation (e.g., mean or high percentile points), and quantify the impact of rising process variations on these power minimization techniques.

Published in:

Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2004