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A chip-level electrostatic discharge simulation strategy

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4 Author(s)
Haifeng Qian ; Minnesota Univ., Minneapolis, MN, USA ; Kozhaya, J.N. ; Nassif, S.R. ; Sapatnekar, S.S.

This work presents a chip-level charged device model (CDM) electrostatic discharge (ESD) simulation method. The chip-level simulation is formulated as a DC analysis problem. A network reduction algorithm based on random walks is proposed for rapid analysis, and to support incremental design. A benchmark with a 2.3M-node VDD net and 1000 I/O pads is checked in 13 minutes, and 10 re-simulations for incremental changes take a total of 9 minutes.

Published in:

Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2004

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