By Topic

Automatic translation of behavioral testbench for fully accelerated simulation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Young-Il Kim ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea ; Chong-Min Kyung

This work presents the automated process of translating behavioral testbench into synthesizable one for the hardware-accelerated simulation. Testbench is mainly implemented in unsynthesizable HDL description such as time delay, event control, non-static loops and sequential statements. Nonetheless, FPGA-based accelerator is limited to synthesizable design. To apply hardware acceleration to behavioral testbench, the proposed method automatically translates testbench into equivalent hardware by emulating the standard simulation reference model. By mapping testbench into hardware accelerator to be merged with the design under verification, we can accelerate behavioral testbench and remove the communication overhead between the software simulator and hardware accelerator. Our experiments demonstrated that the simulation time is reduced by a factor of about 1000 as compared to the conventional hardware accelerated simulation.

Published in:

Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on

Date of Conference:

7-11 Nov. 2004