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A novel identification technique for lumped models of general electronic circuits (i.e. MOSFET, BJT, monolithic integrated circuits and filters) is presented. The approach is based on a neural network having a supplementary layer and an adapted learning process, whose convergence allows the validation of the device model. The supplementary layer is another neural network trained off-line on the model under exam. The inputs of the network are geometrical parameters and the neural network output represents the lumped circuit parameter estimation.