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We propose a new fast learning algorithm for SOM and its digital hardware design based on the massively parallel architecture. When this proposed algorithm is realized by using Xilinx XC2V6000-6 FPGA, a maximum performance of 17500 MCUPS is achieved and up to 256 competing units (16 × 16 map) can be implemented. Each competing unit have a weight vector which is represented by 128 elements of 16 bits accuracy. Furthermore, we applied the proposed hardware to a realtime digital image enlargement system. In the case of full color (24 bits) image enlargement from QQVGA (160 × 120 pixel) to QVGA (320 × 240 pixel), a proposed hardware requires only 0.12 second per image, while the personal computer (Intel XEON, 2.8 GHz Dual) requires more than 5 seconds per image.
Neural Networks, 2004. Proceedings. 2004 IEEE International Joint Conference on (Volume:4 )
Date of Conference: 25-29 July 2004