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We describe the hardware implementation of a Hamming classifier using an optoelectronic architecture. It is composed of two layers, the first layer is an optoelectronic matrix-vector multiplier based on the optical broadcast architecture; it is a novel architecture composed of a set of electronic neurons that receive the input sequentially by means of an optical broadcast interconnection. The second layer is an electronic winner take all circuit. The main characteristic of the system is that it is readily scalable in speed and size to large numbers of pixel neurons. We will describe the optoelectronic architecture, the hardware implementation of a prototype and evaluation of its performance characteristics.