Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process

An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution of small ferroelectric capacitors (< 0.2 /spl mu/m/sup 2/) was measured after fabrication and bake. A reasonable amount of property degradation after 6000hr 125/spl deg/C bake was observed.