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Embedded ferroelectric memory using a 130-nm 5 metal layer Cu / FSG logic process

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17 Author(s)
Summerfelt, S. ; Si Technol. Dev., Texas Instrum., Dallas, TX, USA ; Aggarwal, S. ; Boku, K. ; Celii, F.
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An embedded ferroelectric memory (FRAM) has been developed using a 1.5V, 130nm 5 metal layer Cu / FSG logic process. The only modification to the logic process was the addition of a ferroelectric process consisting of two additional masks (FECAP, VIA0) immediately before MET1. The ferroelectric was 70nm Pb(Zr,Ti)O3 (PZT) deposited by metalorganic chemical vapor deposition (MOCVD). The bit distribution of small ferroelectric capacitors (< 0.2 μm2) was measured after fabrication and bake. A reasonable amount of property degradation after 6000hr 125°C bake was observed.

Published in:

Non-Volatile Memory Technology Symposium, 2004

Date of Conference:

15-17 Nov. 2004

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