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A smart-sensor VLSI circuit suitable for focal-plane low-level image processing applications is presented. The architecture of the device is based on a fine-grain software-programmable SIMD processor array. Processing elements, integrated within each pixel of the imager, are implemented utilising a switched-current analog microprocessor concept. This allows the achievement of real-time image processing speeds with high efficiency in terms of silicon area and power dissipation. The prototype 21 × 21 vision chip is fabricated in a 0.6 μm CMOS technology and achieves a cell size of 98.6 μm × 98.6 μm. It executes over 1.1 giga instructions per second (GIPS) while dissipating under 40 mW of power. The architecture, circuit design and experimental results are presented in this paper.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:52 , Issue: 1 )
Date of Publication: Jan. 2005