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Modeling and simulation for crosstalk aggravated by weak-bridge defects between on-chip interconnects

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3 Author(s)
Lei Wang ; Dept. of EE Syst., Southern California Univ., Los Angeles, CA, USA ; Gupta, S.K. ; Breuer, M.A.

This paper presents comprehensive analytic models that consider both the case of a weak bridge, and the combination of a weak bridge and crosstalk between two interconnects. Our models capture the induced signal delay and pulse as a function of the parameters of the circuit and input signals. Our results are compared with HSPICE and shown to be accurate. A simulator is developed that implements our models and accurately captures timing (delay) characteristics of a circuit. We contrast our results with others, and show the benefits of this new model as well as the ability to predict the range of resistance that leads to delay errors.

Published in:

Test Symposium, 2004. 13th Asian

Date of Conference:

15-17 Nov. 2004