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This paper reports the design of an efficient test set generator (TSG) for VLSI circuit. It is built around the regular structure of cellular automata (CA) employing nonlinear CA rules and targets detection of hard-to-detect pseudo-random pattern resistant faults. The optimal design of TSG structure is achieved with the framework of SA (simulated annealing) to ensure proper selection of CA rules for TSG cells. Efficiency of TSG in comparison to linear CA/LFSR based designs is validated through experimentation.