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Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networks

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3 Author(s)
Bryan, M.J. ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; Devadas, S. ; Keutzer, K.

The authors address the problem of synthesizing circuits that are highly testable for transistor stuck-open fault testability in arbitrary, multilevel networks. They consider single stuck-open faults that are detectable using two-pattern tests, under a robust fault model wherein hazards, races, or glitches cannot invalidate a test. Using these results the authors show that algebraic factorization, including the constrained use of the complement, can be used to synthesize fully-stuck-open-fault testable multilevel networks. They provide a comprehensive set of practical results

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:11 ,  Issue: 6 )