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Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits

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2 Author(s)
D. C. Ku ; Center for Integrated Syst., Stanford Univ., CA, USA ; G. De Mitcheli

For the synthesis of ASIC design that interface with external signals and events, timing constraints and operations with unbounded delays, i.e. delays unknown at compile time, must be considered. The authors present a relative scheduling formulation that supports operations with fixed and unbounded delays. The start time of an operation is specified in terms of offsets from the set of unbounded delay operations called anchors. The authors analyze a property, called well-posedness, of timing constraints. It is used to identify consistency of constraints in the presence of unbounded delay operations. The authors present an algorithm that will transform an ill-posed constraint graph into a minimally serialized well-posed constraint graph, if one exists. The anchors are then checked for redundancy, and they identify the minimum set of anchors that are required in computing the start time. They present an algorithm that schedules the operations relative to the anchors and yields a minimum schedule that satisfies the timing constraints, or detects whether no schedule exists, in polynomial time. They describe the generation of control logic from the resulting relative schedule

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:11 ,  Issue: 6 )