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A hierarchical compiled code event-driven logic simulator

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1 Author(s)
Lewis, D.M. ; Dept. of Electr. Eng., Toronto Univ., Ont., Canada

Logic simulation techniques that reduce both preprocessing time and execution time of unit delay logic simulation are described. Compiled code implementation techniques using a threaded code organization are applied to the event-driven logic simulation algorithm. Simulation speed is increased by a factor of tip to 10 by this technique compared to conventional event-driven simulation. The technique is then extended to hierarchical simulation, in which a fan-out procedure and simulation procedure are generated for each unique module. Hierarchical simulation reduces preprocessing time and allows the recompilation of only those modules that are modified. The simulator uses a portable machine model in which an architecture file describes the target machine. The simulator can be quickly ported to new machines by defining the architecture, while still obtaining high performance

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:10 ,  Issue: 6 )