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Millimeter-wave CMOS design

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4 Author(s)
Doan, C.H. ; Berkeley Wireless Res. Center, Univ. of California, Berkeley, CA, USA ; Emami, S. ; Niknejad, A.M. ; Brodersen, R.W.

This paper describes the design and modeling of CMOS transistors, integrated passives, and circuit blocks at millimeter-wave (mm-wave) frequencies. The effects of parasitics on the high-frequency performance of 130-nm CMOS transistors are investigated, and a peak fmax of 135 GHz has been achieved with optimal device layout. The inductive quality factor (QL) is proposed as a more representative metric for transmission lines, and for a standard CMOS back-end process, coplanar waveguide (CPW) lines are determined to possess a higher QL than microstrip lines. Techniques for accurate modeling of active and passive components at mm-wave frequencies are presented. The proposed methodology was used to design two wideband mm-wave CMOS amplifiers operating at 40 GHz and 60 GHz. The 40-GHz amplifier achieves a peak |S21| = 19 dB, output P1dB = -0.9 dBm, IIP3 = -7.4 dBm, and consumes 24 mA from a 1.5-V supply. The 60-GHz amplifier achieves a peak |S21| = 12 dB, output P1dB = +2.0 dBm, NF = 8.8 dB, and consumes 36 mA from a 1.5-V supply. The amplifiers were fabricated in a standard 130-nm 6-metal layer bulk-CMOS process, demonstrating that complex mm-wave circuits are possible in today's mainstream CMOS technologies.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 1 )

Date of Publication:

Jan. 2005

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