Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation

Notice of Violation of IEEE Publication Principles

"A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation"
by Maxim, A.
in the IEEE Journal of Solid-State Circuits,
Volume 40, Issue 1, Jan. 2005 Page(s):110 - 131

After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.

Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:

C. Turinici, D. Smith, S. Dupue

Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.

Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.

Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.
This paper presents a multigigahertz active clock deskewing architecture that uses analog phase interpolation to replace the area-consuming capacitively controlled delay lines used in regional clock deskewing delay-locked loops. It provides a small phase step that is uniform and process-independent over the entire 2ϖ phase deskew range, which reduces the intra-die clock skew. The phase interpolators have virtually zero latency, which leads to a very fast clock deskewing process and allows for the tracking of fast dynamic variations. A bandgap referencing technique was used to provide a tracking mechanism between the phase-locked loop (PLL) time constants to achieve a process-independent PLL damping factor and pole-zero separation. Both feedback and input divider modulus independence of the damping factor was achieved through a combined current and capacitor switching architecture, that provides an optimal compromise between area, power, and spurs. A reset-generation charge-pump architecture was introduced to minimize the dead-zone avoidance pulse width in order to improve the PLL jitter and reference spurs performance. The power supply partitioning exploits the dual gate oxide transistors offered by the current deep-submicron CMOS technologies. The biasing scheme is comprised of a 1.5-V supply for the ring oscillator and digital circuitry for speed considerations, while the analog front-end is biased from a 2.5-V supply to ensure more voltage headroom as required by low-gain oscillators and low-noise loop filters.