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In this paper, the architecture of a complex 128-point FFT processor using parallel and rolling back structure is presented. The FFT VLSI implementation is suitable to ultra wide band (UWB) communication, because it is ensuring data speed greater than 538 Mbps. With the new VLSI technology, the fast speed and low power are also achieved. The FFT can be operated at an even high frequency up to 200 MHz with FPGA while the power consumption is very low (only for 109 mW at 132 MHz). With 4 radix-4 FFT processors, we employ 16 parallel channels to lower down the operation clock to 132 MHz with the input data of 538 MHz. The CORDIC twiddles processor is applied to combat the area and speed problem compared to a multiplier, so that FFT only has 53 K equivalent gates without sacrificing the data processing speed and throughput.