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Gain-enhanced LDD NMOS device using cesium implantation

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3 Author(s)
Pfiester, J.R. ; Motorola Inc., Austin, TX, USA ; Alvis, J.R. ; Gunderson, C.D.

A gain-enhanced LDD NMOS device has been developed for a submicrometer CMOS technology. Using cesium implantation to create a fixed positive charge at the oxide/silicon interface above the LDD region, improvements in device gain are obtained without degradation to hot-carrier reliability or short-channel behavior. Since fixed charge rather than an extended polysilicon gate is used to overlap the LDD regions, no penalty is paid in terms of extra gate overlap capacitance. Furthermore, this structure is easily integrated into a conventional twin-tub CMOS process with the addition of only one cesium implantation step which is performed at the same time as the LDD n- implant step

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Electron Devices, IEEE Transactions on  (Volume:39 ,  Issue: 6 )