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Advanced process device technology for 0.3-μm high-performance bipolar LSIs

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5 Author(s)
Tamaki, Y. ; Hitachi Ltd., Tokyo, Japan ; Shiba, T. ; Kure, T. ; Ohyu, Kiyonori
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A new method is developed for forming shallow emitter/bases, collectors, and graft bases suitable for high-performance 0.3-μm bipolar LSIs. Fabricated 0.5-μm U-SICOS (U-groove isolated sidewall base contact structure) transistors are 44 μm2, and they have an isolation width of 2.0 μm, a minimum emitter width of 0.2 μm, a maximum cutoff frequency (fT) of 50 GHz, and a minimum ECL gate delay time of 27 ps. The key points for fabricating high-performance 0.3-μm bipolar LSIs are the control of the graft base depth and the control of the interfacial layer between emitter poly-Si and single-Si. The importance of a tradeoff relation between fT and base resistance is also discussed

Published in:

Electron Devices, IEEE Transactions on  (Volume:39 ,  Issue: 6 )

Date of Publication:

Jun 1992

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