Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Babighian, P. ; Politecnico di Torino, Italy ; Benini, L. ; Macii, E.

We propose a new algorithm for automatic clock-gating insertion applicable at the register transfer level (RTL). The basic rationale of our approach is to eliminate redundant computations performed by temporally unobservable blocks through aggressive exploitation of observability don't care (ODC) conditions. ODCs are efficiently detected from an RTL description by focusing only on data-path modules with easily detectable input unobservability conditions. ODCs are then propagated in the form of logic expressions toward the registers by backward traversal and levelization of the design. Finally, the logic expressions are mapped onto hardware to provide control signals to the clock-gating logic at a reduced cost in area and speed. The technique is characterized by fast processing time, high scalability to large designs, and tight user control on clock-gating overhead. Our approach is compatible with standard industrial design flows, and reduces power consumption significantly with a small overhead in delay and area. Experimental results obtained on a set of industrial RTL designs containing several tens of thousands of gates show average power reductions of around 42%. On the same examples, the application of traditional clock-gating leads to average savings reductions close to 29%.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:24 ,  Issue: 1 )