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The paper presents a new architecture for systems based on run-time reconfigured shared memory processor clusters meant for implementation using network on chip technology. Clusters constitute local data exchange sub-networks, which dynamically connect processors with shared memory modules. The sub-networks enable exposure of data from one processor's data cache for reading by other processors to their data caches. This inter-processor data exchange paradigm, called "communication on the fly", enables direct communication between processor data caches. Dual-ported data caches are assumed to enable parallel reading and writing data between the caches and memory modules. In the proposed architecture, programs are executed according to a cache-controlled macro data flow execution model. Computational tasks are so defined, as to eliminate re-loading of data caches during task execution. A special program macro-data flow graph representation enables modeling of program behaviour for different architectural and program structure assumptions. Simulation results of symbolic execution of program graphs of matrix multiplication are presented in the paper. They show suitability of the proposed architecture for very fine grain parallel computations.
Parallel and Distributed Computing, 2004. Third International Symposium on/Algorithms, Models and Tools for Parallel Computing on Heterogeneous Networks, 2004. Third International Workshop on
Date of Conference: 5-7 July 2004