By Topic

Impact of scaling on the high current behavior of RF CMOS technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Boselli, G. ; Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA ; Reddy, V. ; Duvvury, C.

In this paper, the impact of the starting material resistivity on the electrostatic discharge (ESD), latch-up, and injection induced breakdown voltage (BVii) sensitivity will be investigated for a sub-100-nm fully silicided CMOS technology for low-power and RF applications. The mechanisms through which the increase of the substrate spreading resistance enhances the uniformity of the ESD current in nMOS-based protection methods will be investigated in detail. Tradeoffs between ESD, latch-up, and BVii will be addressed as well.

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:4 ,  Issue: 3 )