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Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling

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8 Author(s)
Mielke, N. ; Intel Corp., Santa Clara, CA, USA ; Belgal, H. ; Kalastirsky, I. ; Kalavade, P.
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Charge trapping over the channel can occur from program/erase cycling of Flash memory cells, increasing the cell threshold voltage and causing threshold shifts in retention tests when charges detrap. The empirical characteristics of these effects are discussed. Trapping has a square-root dependence on program/erase cycle count. Detrapping scales with the logarithm of time and is thermally accelerated with an activation energy of 1.1 to 1.2 eV. Detrapping has only a weak dependence on electric field. These mechanisms are intrinsic, yet there is a wide variation in behavior from one cell to another related to Poisson statistical variations. Common reliability characterization methods need to be re-thought in light of the characteristics of this and other mechanisms. In particular, performing extensive program/erase cycling with no delays between cycles is unrealistic for this mechanism, and alternative distributed-cycling schemes are proposed.

Published in:

Device and Materials Reliability, IEEE Transactions on  (Volume:4 ,  Issue: 3 )

Date of Publication:

Sept. 2004

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