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A novel implementation of a high frequency divider using a synchronized quadrature LC oscillator is discussed in this paper. This presented approach solves the problem of I/Q signal generation with the aid of frequency division. Through simulation it was shown that this solution exhibits two different locking ranges each possessing a bandwidth of 20% of the given input frequency. When using a 6-bit variable capacitor the divider is capable of working within a 5 GHz frequency range, therefore making it suitable for ultra wideband systems. The proposed divider exhibits low power consumption, low sensitivity to input phase error, amplitude swing and DC level.