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A high resolution, extended temperature sigma delta ADC in 3.3 V 0.5 μm SOS-CMOS

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7 Author(s)

A ΣΔ modulator designed specifically for extended temperature applications is reported. The design is fabricated in a 3.3-V 0.5 μm SOS-CMOS process and incorporates a 2-2 cascade architecture allowing operation as either a 2nd- or 4th-order modulator. Experimental data for both modulator configurations are presented including dynamic range (or effective resolution), signal-to-noise ratio and total harmonic distortion over a temperature range of 25°C to 225°C. The design obtains an effective resolution of ∼16 bits at 25°C and ∼12 bits at 225°C, both at a digital output rate of 2 KS/s. Specific design details associated with high temperature operation are discussed including architectural issues, device sizing, and modulator noise. In addition, a digital decimation filter designed for use with the modulator and implemented in both software and in a field programmable gate array is summarized. This paper reports the first 4th-order ΣΔ modulator fabricated in an SOI/SOS process and demonstrates the feasibility of high resolution data conversion at elevated temperatures.

Published in:

Aerospace Conference, 2004. Proceedings. 2004 IEEE  (Volume:4 )

Date of Conference:

13-13 March 2004