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There is a tremendous need for space-qualified high-performance processing hardware. This need is being driven by increased sensor data rates in systems with limited downlink capacity, and a desire for autonomous operation. Traditional processing elements such as ASICs and sequential processors are less than ideal for high-performance processing. SRAM-based FPGAs offer the highest processing performance available in a flexible, reprogrammable, and low risk space-qualified device. However, the use of SRAM-based FPGAs in space applications can also be challenging. This paper discusses the design of FPGA-based reconfigurable computing (RCC) hardware for space. It discusses the processing capability of the given architecture, and gives performance metrics for typical applications. Radiation effect mitigation techniques are discussed, and upset rates are given for different levels of mitigation. Finally, the development cycle for typical applications is addressed, including an overview of the tools that are available to implement processing algorithms and upset mitigation techniques.