Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

Configurable fault-tolerant processor (CFTP) for spacecraft onboard processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hulme, C.A. ; Naval Postgraduate Sch., Monterey, CA, USA ; Loomis, H.H. ; Ross, A.A. ; Rong Yuan

The harsh radiation environment of space, the propensity for SEUs to perturb the operations of silicon-based electronics, the rapid development of microprocessor capabilities and hence software applications, and the high cost (dollars and time) to develop and prove a system, require flexible, reliable, low cost, rapidly developed system solutions. A reconfigurable triple-modular-redundant (TMR) system-on-a-chip (SOC) utilizing field-programmable gate arrays (FPGAs) provides a practical solution for space-based systems. The configurable fault-tolerant processor (CFTP) is such a system, designed specifically for the purpose of testing and evaluating, on orbit, both the reliability of instantiated TMR soft-core microprocessors, the ability to reconfigure the system to support any onboard processor function, and the means for detecting and correcting SEU-induced configuration faults. The CFTP utilizes commercial off-the-shelf (COTS) technology to investigate a low-cost, flexible alternative to processor hardware architecture, with a total-ionizing-dose (TID) tolerant FPGA as the basis for a SOC. The flexibility of a configurable processor, based on FPGA technology, enables on-orbit upgrades, reconfigurations, and modifications to the soft-core architecture in order to support dynamic mission requirements. Single event upsets (SEU) to the data stored in the FPGA-based soft-core processors are detected and corrected by the TMR architecture. SEUs affecting the FPGA configuration itself are corrected by background "scrubbing" of the configuration. The CFTP payload consists of a printed circuit board (PCB) of 5.3 inches×7.3 inches utilizing a slightly modified PC/104 bus interface. The initial FPGA configuration is an instantiation of a TMR processor, with included error detection and correction (EDAC) and memory controller circuitry. The PCB is designed with requisite supporting circuitry including a configuration controller FPGA, SDRAM, and flash memory in order to allow the greatest variety of possible configurations. The CFTP is currently manifested as a space test program (STP) experimental payload on the Naval Postgraduate School's NPSAT1 and the United States Naval Academy's MidSTAR-1 satellites, which was launched into low earth orbit in March 2003- .

Published in:

Aerospace Conference, 2004. Proceedings. 2004 IEEE  (Volume:4 )

Date of Conference:

6-13 March 2004