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Robust tests for stuck-open faults and design for testability of reconvergent fan-out CMOS logic networks

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2 Author(s)
Darlay, F. ; IMAG/TIM3 Lab., Grenoble, France ; Courtois, B.

This paper addresses the problem of generating robust tests (tests which are efficient even in the presence of arbitrary delays) for stuck-open faults, in CMOS logic networks. The authors' approach consists of a topological analysis leading to the definition of a criterion which allows them to distinguish between robustly and non-robustly testable gates. They also present a new design for testability method, to be applied to non-robustly testable gates

Published in:

Design Automation Conference, 1990., EDAC. Proceedings of the European

Date of Conference:

12-15 Mar 1990