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A static frequency divider with a maximum clock frequency >150 GHz was designed and fabricated in a narrow mesa InP/In0.53Ga0.47As/InP DHBT technology. The divider operation is fully static, operating from fdk = 3 GHz to 152.0 GHz while dissipating 594.7 mW of power in the circuit core from a -4.07 V supply. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. The transistors have an emitter junction width of 0.5 μm and a 3.0 collector-to-emitter area ratio. A microstrip wiring environment is employed for high interconnect density, and to minimize resonances and impedance mismatch at frequencies >100 GHz.